The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as the geometry sizes shrink, it generally becomes difficult for conventional photolithography processes to form semiconductor features having these small sizes. One approach to this issue uses a double patterning (DP) method. A typical DP method decomposes an IC layout into two subsets and fabricates a photomask for each subset. A wafer is patterned with the two photomasks in two lithography processes. Images of the two lithography processes overlay with one another to collectively produce a denser image on the wafer. In traditional DP methods, the two lithography processes have the same resolution, which in some cases limits the minimum critical dimension (CD) that can be produced by the DP methods. Improvements in these areas are desired.